FPGA项目实战：手把手教你用Verilog实现一个高效的图像旋转IP核

// 顶层模块接口示例
module image_rotate_top #(
    parameter IMG_W = 640,
    parameter IMG_H = 480,
    parameter DATA_W = 8,
    parameter ANGLE_W = 16
) (
    input  wire                 clk,
    input  wire                 rst_n,
    // AXI4-Stream Slave 接口 (输入图像)
    input  wire [DATA_W-1:0]    s_axis_tdata,
    input  wire                 s_axis_tvalid,
    output wire                 s_axis_tready,
    input  wire                 s_axis_tlast,
    // AXI4-Stream Master 接口 (输出图像)
    output wire [DATA_W-1:0]    m_axis_tdata,
    output wire                 m_axis_tvalid,
    input  wire                 m_axis_tready,
    output wire                 m_axis_tlast,
    // 控制接口：旋转角度设置 (定点数，Q1.15格式)
    input  wire [ANGLE_W-1:0]   rotation_angle
);

// 单级CORDIC流水线单元 (旋转模式，圆周系统)
module cordic_stage #(
    parameter STAGE_IDX = 0,
    parameter DATA_W = 18,
    parameter ANGLE_W = 16
) (
    input  wire signed [DATA_W-1:0] xi, yi,
    input  wire signed [ANGLE_W-1:0] zi,
    output reg  signed [DATA_W-1:0] xo, yo,
    output reg  signed [ANGLE_W-1:0] zo
);
    // 预计算的arctan(2^{-i})值，Q1.15格式
    localparam signed [ANGLE_W-1:0] ANGLE_LUT = `get_angle(STAGE_IDX);

    wire di = (zi >= 0); // 旋转方向判断
    wire signed [DATA_W-1:0] xi_shifted = xi >>> STAGE_IDX; // 算术右移
    wire signed [DATA_W-1:0] yi_shifted = yi >>> STAGE_IDX;

    always @(*) begin
        if (di) begin // 正向旋转
            xo = xi - yi_shifted;
            yo = yi + xi_shifted;
            zo = zi - ANGLE_LUT;
        end else begin // 反向旋转
            xo = xi + yi_shifted;
            yo = yi - xi_shifted;
            zo = zi + ANGLE_LUT;
        end
    end
endmodule

# rotate.xdc 关键约束片段
# 主时钟约束 (假设从引脚clk_pin输入)
create_clock -name clk -period 10.0 [get_ports clk_pin]

# 虚拟时钟约束，用于设定输入输出延迟（如果接口是异步的）
create_clock -name vclk -period 10.0

# 输入延迟约束 (假设数据在时钟沿后2ns稳定)
set_input_delay -clock vclk -max 2.0 [get_ports {s_axis_tdata s_axis_tvalid s_axis_tlast}]
set_input_delay -clock vclk -min 0.5 [get_ports {s_axis_tdata s_axis_tvalid s_axis_tlast}]

# 输出延迟约束
set_output_delay -clock vclk -max 3.0 [get_ports {m_axis_tdata m_axis_tvalid m_axis_tlast}]
set_output_delay -clock vclk -min -1.0 [get_ports {m_axis_tdata m_axis_tvalid m_axis_tlast}]

# 伪路径约束（如角度配置信号在运行期间不变）
set_false_path -to [get_ports rotation_angle]

// 测试平台关键任务：从文件读取图像并驱动AXI-Stream接口
task automatic drive_image_input(string filename);
    integer fd, code;
    logic [7:0] pixel;
    fd = $fopen(filename, "rb");
    if (!fd) begin $error("File open failed"); $finish; end
    s_axis_tvalid <= 1'b0;
    @(posedge clk);
    for (int y = 0; y < IMG_H; y++) begin
        for (int x = 0; x < IMG_W; x++) begin
            code = $fread(pixel, fd);
            s_axis_tdata <= pixel;
            s_axis_tvalid <= 1'b1;
            s_axis_tlast <= (x == IMG_W-1);
            do begin
                @(posedge clk);
            end while (s_axis_tready !== 1'b1); // 等待握手
        end
    end
    s_axis_tvalid <= 1'b0;
    $fclose(fd);
endtask