Verilog Testbench自动化：利用Python脚本生成激励与解析仿真结果

project/
├── rtl/               # 设计文件 (.v)
├── tb/                # Testbench 文件 (.v)
├── scripts/           # Python 脚本
│   ├── gen_stimulus.py
│   ├── parse_results.py
│   └── run_flow.py    # 主控脚本
├── sim/               # 仿真运行目录（可自动生成）
│   ├── stimulus.txt   # 生成的激励
│   ├── sim_output.log # 仿真原始输出
│   └── report.txt     # 最终解析报告
└── run_sim.sh         # 可选的 Shell 入口

import random

def generate_random_stimulus(num_tests=1000, data_width=8):
    """生成随机激励文件，格式：每行一个十六进制数"""
    with open('sim/stimulus.txt', 'w') as f:
        for _ in range(num_tests):
            a = random.randint(0, (1<<data_width)-1)
            b = random.randint(0, (1<<data_width)-1)
            # 约定：一行包含两个输入，以空格或逗号分隔
            f.write(f"{a:04x} {b:04x}
")  # 04x表示4位十六进制

def generate_directed_stimulus():
    """生成边界情况或定向测试向量"""
    directed_cases = [
        (0, 0),
        (255, 0),
        (0, 255),
        (255, 255),
        (1, 254)
    ]
    with open('sim/stimulus.txt', 'w') as f:
        for a, b in directed_cases:
            f.write(f"{a:04x} {b:04x}
")

if __name__ == "__main__":
    # 可以添加命令行参数解析，方便选择模式
    generate_random_stimulus(1000)

`timescale 1ns/1ps
module tb_adder;
    reg  [7:0] a, b;
    wire [8:0] sum;
    integer i, file_in, file_out;
    reg  [15:0] stimulus [0:999]; // 假设最多1000个激励对

    adder uut (.a(a), .b(b), .sum(sum));

    initial begin
        // 1. 打开激励文件和输出日志文件
        file_in = $fopen("sim/stimulus.txt", "r");
        if (!file_in) begin $display("Error opening stimulus file"); $finish; end
        file_out = $fopen("sim/sim_output.log", "w");
        
        // 2. 读取激励（方法一：逐行读取解析）
        // while (!$feof(file_in)) begin
        //     // 使用 $fscanf 按格式读取
        // end
        
        // 2. 读取激励（方法二：一次性读入数组，需提前知道数量）
        $readmemh("sim/stimulus.txt", stimulus);
        
        // 3. 应用激励并记录结果
        for (i = 0; i < 1000; i = i + 1) begin
            {a, b} = stimulus[i]; // 根据生成格式解包
            #10; // 等待稳定
            // 写入日志：时间、输入a、输入b、输出sum
            $fdisplay(file_out, "%t, %h, %h, %h", $time, a, b, sum);
        end
        
        // 4. 关闭文件并结束仿真
        $fclose(file_in);
        $fclose(file_out);
        $display("Simulation finished. Log saved to sim_output.log");
        $finish;
    end
endmodule

import re

def parse_and_check(log_file='sim/sim_output.log'):
    error_count = 0
    error_list = []
    
    with open(log_file, 'r') as f:
        for line_num, line in enumerate(f, 1):
            line = line.strip()
            if not line:
                continue
            # 解析日志行，例如："10000, 0a, 1b, 025"
            # 正则匹配：时间，十六进制a，十六进制b，十六进制sum
            match = re.match(r'(\d+),\s*(\w+),\s*(\w+),\s*(\w+)', line)
            if not match:
                print(f"Warning: Cannot parse line {line_num}: {line}")
                continue
                
            sim_time, a_hex, b_hex, sum_hex = match.groups()
            a = int(a_hex, 16)
            b = int(b_hex, 16)
            sum_sim = int(sum_hex, 16)
            
            # 黄金模型计算（这里是8位加法器）
            sum_expected = a + b
            # 注意：实际硬件是9位输出，我们只取低9位比较
            mask = (1 << 9) - 1
            sum_expected_masked = sum_expected & mask
            
            # 比对
            if sum_sim != sum_expected_masked:
                error_count += 1
                error_list.append({
                    'line': line_num,
                    'time': sim_time,
                    'input_a': a_hex,
                    'input_b': b_hex,
                    'expected': f'{sum_expected_masked:03x}',
                    'got': sum_hex
                })
    
    # 生成报告
    with open('sim/report.txt', 'w') as report:
        report.write(f"=== Simulation Result Report ===
")
        report.write(f"Total tests checked: {line_num}
")
        report.write(f"Errors found: {error_count}
")
        report.write(f"Pass rate: {(line_num - error_count)/line_num*100:.2f}%

")
        
        if error_list:
            report.write("Error Details:
")
            for err in error_list:
                report.write(f"  Line {err['line']} @{err['time']}ps: ")
                report.write(f"a={err['input_a']}, b={err['input_b']}, ")
                report.write(f"expected={err['expected']}, got={err['got']}
")
    
    # 控制台输出摘要
    if error_count == 0:
        print(f"\033[92mPASS! All {line_num} tests passed.\033[0m")
        return True
    else:
        print(f"\033[91mFAIL! {error_count} errors found. See report.txt for details.\033[0m")
        return False

if __name__ == "__main__":
    parse_and_check()

import os
import sys
import subprocess
import shutil
from gen_stimulus import generate_random_stimulus
from parse_results import parse_and_check

def run_simulation():
    """调用仿真器编译和运行"""
    # 1. 编译
    compile_cmd = ['iverilog', '-o', 'sim/adder_tb.vvp',
                   '-Irtl', '-Itb', 'rtl/adder.v', 'tb/tb_adder.v']
    print("Compiling...")
    result = subprocess.run(compile_cmd, capture_output=True, text=True)
    if result.returncode != 0:
        print("Compilation failed:")
        print(result.stderr)
        return False
    
    # 2. 运行仿真
    sim_cmd = ['vvp', 'sim/adder_tb.vvp']
    print("Running simulation...")
    result = subprocess.run(sim_cmd, capture_output=True, text=True)
    print(result.stdout)  # 打印仿真器输出信息
    if result.returncode != 0:
        print("Simulation failed:")
        print(result.stderr)
        return False
    return True

def main():
    # 清理并创建仿真目录
    sim_dir = 'sim'
    if os.path.exists(sim_dir):
        shutil.rmtree(sim_dir)
    os