2026年FPGA工程师必备技能：SystemVerilog验证方法学与UVM实战入门

// rtl/adder.sv - 一个简单的 DUT
module adder #(parameter WIDTH = 8) (
    input  logic                  clk,
    input  logic                  rst_n,
    input  logic [WIDTH-1:0]      a,
    input  logic [WIDTH-1:0]      b,
    input  logic                  valid_i,
    output logic [WIDTH-1:0]      sum,
    output logic                  valid_o
);
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            sum <= '0;
            valid_o <= 1'b0;
        end else if (valid_i) begin
            sum <= a + b;
            valid_o <= 1'b1;
        end else begin
            valid_o <= 1'b0;
        end
    end
endmodule

// tb/adder_transaction.sv
class adder_transaction extends uvm_sequence_item;
    rand bit [7:0] a;
    rand bit [7:0] b;
    bit [7:0] sum;
    rand bit delay; // 用于插入空闲周期

    constraint c_valid { a < 8'h80; b < 8'h80; } // 防止溢出，简化检查
    constraint c_delay { delay inside {[0:3]}; }

    `uvm_object_utils_begin(adder_transaction)
        `uvm_field_int(a, UVM_ALL_ON)
        `uvm_field_int(b, UVM_ALL_ON)
        `uvm_field_int(sum, UVM_ALL_ON)
        `uvm_field_int(delay, UVM_ALL_ON)
    `uvm_object_utils_end

    function new(string name = "adder_transaction");
        super.new(name);
    endfunction
endclass

// tb/adder_if.sv
interface adder_if(input logic clk, input logic rst_n);
    logic [7:0] a;
    logic [7:0] b;
    logic       valid_i;
    logic [7:0] sum;
    logic       valid_o;

    // Driver 侧时钟块，在时钟上升沿后驱动
    clocking drv_cb @(posedge clk);
        default input #1ns output #1ns; // 避免时钟沿竞争
        output a, b, valid_i;
        input sum, valid_o;
    endclocking

    // Monitor 侧时钟块，在时钟上升沿前采样
    clocking mon_cb @(posedge clk);
        default input #1ns;
        input a, b, valid_i, sum, valid_o;
    endclocking

    modport DRV  (clocking drv_cb, input clk, rst_n);
    modport MON  (clocking mon_cb, input clk, rst_n);
    modport DUT  (input a, b, valid_i, output sum, valid_o, input clk, rst_n);
endinterface

// tb/adder_driver.sv (片段)
virtual task run_phase(uvm_phase phase);
    forever begin
        seq_item_port.get_next_item(req); // 从 sequencer 获取事务
        drive_transfer(req); // 将事务驱动到 DUT 接口
        seq_item_port.item_done(); // 告知 sequencer 当前事务处理完毕
    end
endtask

task drive_transfer(adder_transaction trans);
    @(vif.drv_cb); // 等待时钟沿
    vif.drv_cb.valid_i <= 1'b0; // 默认无效
    repeat(trans.delay) @(vif.drv_cb); // 插入延迟
    vif.drv_cb.a <= trans.a;
    vif.drv_cb.b <= trans.b;
    vif.drv_cb.valid_i <= 1'b1;
    @(vif.drv_cb);
    vif.drv_cb.valid_i <= 1'b0;
endtask

// tb/adder_scoreboard.sv (核心方法)
virtual function void write_mon(adder_transaction trans);
    adder_transaction exp_trans;
    // 从预期队列中取出
    if (exp_queue.size() > 0) begin
        exp_trans = exp_queue.pop_front();
        if (exp_trans.sum != trans.sum) begin // 简单比较
            `uvm_error("SCBD", $sformatf("Mismatch! Exp: 0x%0h, Got: 0x%0h", exp_trans.sum, trans.sum))
        end else begin
            `uvm_info("SCBD", $sformatf("Match OK: 0x%0h", trans.sum), UVM_LOW)
        end
    end else begin
        `uvm_error("SCBD", "Unexpected transaction received from monitor")
    end
endfunction