Groq 3 LPU 首秀：FPGA 在 AI 推理加速器中的新定位——脉动阵列设计实践指南

module systolic_array #(
    parameter ROWS = 4,
    parameter COLS = 4,
    parameter DATA_WIDTH = 8
)(
    input clk,
    input rst_n,
    input [DATA_WIDTH-1:0] data_in_left [0:ROWS-1],
    input [DATA_WIDTH-1:0] data_in_top [0:COLS-1],
    input valid_in,
    output [2*DATA_WIDTH+7:0] data_out_bottom [0:COLS-1],
    output valid_out
);

    genvar i, j;
    generate
        for (i = 0; i < ROWS; i = i + 1) begin : row_loop
            for (j = 0; j < COLS; j = j + 1) begin : col_loop
                wire [DATA_WIDTH-1:0] left_in;
                wire [DATA_WIDTH-1:0] top_in;
                wire [DATA_WIDTH-1:0] left_out;
                wire [DATA_WIDTH-1:0] top_out;
                wire [2*DATA_WIDTH+7:0] partial_sum_in;
                wire [2*DATA_WIDTH+7:0] partial_sum_out;

                if (j == 0) begin
                    assign left_in = data_in_left[i];
                end else begin
                    assign left_in = top_out;  // 注意：此处为简化连接，实际需根据拓扑调整
                end

                if (i == 0) begin
                    assign top_in = data_in_top[j];
                end else begin
                    assign top_in = left_out;
                end

                if (i == 0 && j == 0) begin
                    assign partial_sum_in = 0;
                end else if (j == 0) begin
                    assign partial_sum_in = partial_sum_out;  // 来自上方PE
                end else begin
                    assign partial_sum_in = partial_sum_out;  // 来自左侧PE
                end

                pe #(
                    .DATA_WIDTH(DATA_WIDTH)
                ) u_pe (
                    .clk(clk),
                    .rst_n(rst_n),
                    .data_in_left(left_in),
                    .data_in_top(top_in),
                    .partial_sum_in(partial_sum_in),
                    .data_out_left(left_out),
                    .data_out_top(top_out),
                    .partial_sum_out(partial_sum_out)
                );

                if (i == ROWS-1) begin
                    assign data_out_bottom[j] = partial_sum_out;
                end
            end
        end
    endgenerate

    // valid_out 生成逻辑（简化）
    reg valid_delay;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            valid_delay <= 0;
        else
            valid_delay <= valid_in;
    end
    assign valid_out = valid_delay;

endmodule

module pe #(
    parameter DATA_WIDTH = 8
)(
    input clk,
    input rst_n,
    input [DATA_WIDTH-1:0] data_in_left,
    input [DATA_WIDTH-1:0] data_in_top,
    input [2*DATA_WIDTH+7:0] partial_sum_in,
    output reg [DATA_WIDTH-1:0] data_out_left,
    output reg [DATA_WIDTH-1:0] data_out_top,
    output reg [2*DATA_WIDTH+7:0] partial_sum_out
);

    reg [2*DATA_WIDTH+7:0] acc;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            acc <= 0;
            data_out_left <= 0;
            data_out_top <= 0;
            partial_sum_out <= 0;
        end else begin
            acc <= partial_sum_in + (data_in_left * data_in_top);
            data_out_left <= data_in_left;
            data_out_top <= data_in_top;
            partial_sum_out <= acc;
        end
    end

endmodule

create_clock -period 5.000 -name sys_clk [get_ports clk]
set_input_delay -clock sys_clk -max 2.0 [get_ports data_in_left*]
set_output_delay -clock sys_clk -max 2.0 [get_ports data_out_bottom*]

// 测试平台示例（简化）
module tb_systolic_array;
    reg clk, rst_n;
    reg [7:0] left_data [0:3];
    reg [7:0] top_data [0:3];
    reg valid_in;
    wire [23:0] out_data [0:3];
    wire valid_out;

    systolic_array uut (.*);

    initial begin
        clk = 0;
        forever #2.5 clk = ~clk;
    end

    initial begin
        rst_n = 0;
        #10 rst_n = 1;
        #10;
        left_data = '{8'd1, 8'd2, 8'd3, 8'd4};
        top_data = '{8'd5, 8'd6, 8'd7, 8'd8};
        valid_in = 1;
        #20;
        valid_in = 0;
        #50;
        $finish;
    end

endmodule