Verilog实战：2026年用AXI Stream实现高效数据打包与解包

module pack_8to32 (
    input  wire       clk,
    input  wire       rst_n,
    // AXI Stream 从机接口 (8-bit)
    input  wire [7:0] s_axis_tdata,
    input  wire       s_axis_tvalid,
    output reg        s_axis_tready,
    // AXI Stream 主机接口 (32-bit)
    output reg  [31:0] m_axis_tdata,
    output reg         m_axis_tvalid,
    input  wire        m_axis_tready
);

    reg [1:0] byte_cnt;  // 0..3
    reg [31:0] shift_reg;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            byte_cnt <= 2'd0;
            shift_reg <= 32'd0;
            s_axis_tready <= 1'b0;
            m_axis_tvalid <= 1'b0;
            m_axis_tdata <= 32'd0;
        end else begin
            // 默认：从机就绪（除非主机未就绪且我们正在发送）
            s_axis_tready <= 1'b1;

            // 接收字节
            if (s_axis_tvalid && s_axis_tready) begin
                shift_reg <= {s_axis_tdata, shift_reg[31:8]};
                byte_cnt <= byte_cnt + 1'd1;
            end

            // 当收集满 4 字节，且主机就绪时发送
            if (byte_cnt == 2'd3 && s_axis_tvalid && s_axis_tready) begin
                m_axis_tdata <= {s_axis_tdata, shift_reg[31:8]};
                m_axis_tvalid <= 1'b1;
            end else if (m_axis_tvalid && m_axis_tready) begin
                m_axis_tvalid <= 1'b0;
            end
        end
    end

endmodule

module unpack_32to8 (
    input  wire       clk,
    input  wire       rst_n,
    // AXI Stream 从机接口 (32-bit)
    input  wire [31:0] s_axis_tdata,
    input  wire        s_axis_tvalid,
    output reg         s_axis_tready,
    // AXI Stream 主机接口 (8-bit)
    output reg  [7:0]  m_axis_tdata,
    output reg         m_axis_tvalid,
    input  wire        m_axis_tready
);

    reg [1:0] byte_idx;  // 0..3
    reg [31:0] data_word;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            byte_idx <= 2'd0;
            data_word <= 32'd0;
            s_axis_tready <= 1'b0;
            m_axis_tvalid <= 1'b0;
            m_axis_tdata <= 8'd0;
        end else begin
            // 默认：从机就绪（除非正在发送字节）
            s_axis_tready <= (byte_idx == 2'd0) ? 1'b1 : 1'b0;

            // 如果从机接口有数据且本模块就绪，锁存整个字
            if (s_axis_tvalid && s_axis_tready) begin
                data_word <= s_axis_tdata;
                byte_idx <= 2'd1;  // 立即开始发送第一个字节
            end

            // 发送字节到主机
            if (m_axis_tvalid && m_axis_tready) begin
                if (byte_idx == 2'd3) begin
                    byte_idx <= 2'd0;
                    m_axis_tvalid <= 1'b0;
                end else begin
                    byte_idx <= byte_idx + 1'd1;
                end
            end

            // 更新输出数据与 valid
            if (byte_idx != 2'd0) begin
                m_axis_tdata <= data_word[byte_idx*8 +: 8];
                m_axis_tvalid <= 1'b1;
            end else begin
                m_axis_tvalid <= 1'b0;
            end
        end
    end

endmodule

module tb_pack_unpack;
    reg clk, rst_n;
    reg [7:0]  data_in;
    reg        valid_in;
    wire       ready_in;
    wire [7:0] data_out;
    wire       valid_out;
    reg        ready_out;

    // 例化打包与解包模块
    pack_8to32 u_pack (
        .clk(clk), .rst_n(rst_n),
        .s_axis_tdata(data_in),
        .s_axis_tvalid(valid_in),
        .s_axis_tready(ready_in),
        .m_axis_tdata(pack_to_unpack_data),
        .m_axis_tvalid(pack_to_unpack_valid),
        .m_axis_tready(pack_to_unpack_ready)
    );

    unpack_32to8 u_unpack (
        .clk(clk), .rst_n(rst_n),
        .s_axis_tdata(pack_to_unpack_data),
        .s_axis_tvalid(pack_to_unpack_valid),
        .s_axis_tready(pack_to_unpack_ready),
        .m_axis_tdata(data_out),
        .m_axis_tvalid(valid_out),
        .m_axis_tready(ready_out)
    );

    wire [31:0] pack_to_unpack_data;
    wire        pack_to_unpack_valid;
    wire        pack_to_unpack_ready;

    // 时钟与复位
    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end
    initial begin
        rst_n = 0; #20 rst_n = 1;
    end

    // 激励
    initial begin
        ready_out = 1;
        valid_in = 0;
        #30;
        // 发送 8 个字节：0x01, 0x02, ..., 0x08
        repeat (8) begin
            @(posedge clk);
            valid_in = 1;
            data_in = data_in + 1;
            if (ready_in) @(posedge clk);
        end
        valid_in = 0;
        #100;
        $finish;
    end

    // 监视输出
    initial begin
        $monitor("Time=%0t data_out=%h valid_out=%b", $time, data_out, valid_out);
    end

endmodule