Verilog实战：2026年用流水线加法器优化数字信号处理性能

// rtl/pipeline_adder.v
// 4级流水线加法器，输入a,b均为16位有符号数，输出sum为17位
// 流水线深度：4个时钟周期

module pipeline_adder #(
    parameter DATA_WIDTH = 16
) (
    input  wire                clk,
    input  wire                rst_n,
    input  wire signed [DATA_WIDTH-1:0] a,
    input  wire signed [DATA_WIDTH-1:0] b,
    output reg  signed [DATA_WIDTH:0]   sum
);

    // 流水线寄存器定义
    reg signed [DATA_WIDTH-1:0] a_r1, a_r2, a_r3, a_r4;
    reg signed [DATA_WIDTH-1:0] b_r1, b_r2, b_r3, b_r4;
    reg signed [DATA_WIDTH:0]   sum_r1, sum_r2, sum_r3;

    // 第1级：寄存输入
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            a_r1 <= {DATA_WIDTH{1'b0}};
            b_r1 <= {DATA_WIDTH{1'b0}};
        end else begin
            a_r1 <= a;
            b_r1 <= b;
        end
    end

    // 第2级：寄存输入（继续传递）
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            a_r2 <= {DATA_WIDTH{1'b0}};
            b_r2 <= {DATA_WIDTH{1'b0}};
        end else begin
            a_r2 <= a_r1;
            b_r2 <= b_r1;
        end
    end

    // 第3级：执行加法并寄存结果
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            sum_r1 <= {DATA_WIDTH+1{1'b0}};
        end else begin
            sum_r1 <= a_r2 + b_r2;
        end
    end

    // 第4级：输出寄存器
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            sum <= {DATA_WIDTH+1{1'b0}};
        end else begin
            sum <= sum_r1;
        end
    end

endmodule

# top.xdc
# 主时钟约束
create_clock -period 5.000 -name sysclk [get_ports clk_p]

# 输入延迟约束（假设外部器件驱动数据在时钟上升沿后 1 ns 有效）
set_input_delay -clock sysclk -max 1.0 [get_ports a]
set_input_delay -clock sysclk -max 1.0 [get_ports b]
set_input_delay -clock sysclk -min 0.2 [get_ports a]
set_input_delay -clock sysclk -min 0.2 [get_ports b]

# 输出延迟约束（假设外部器件在时钟上升沿前 0.5 ns 需要数据稳定）
set_output_delay -clock sysclk -max 0.5 [get_ports sum]
set_output_delay -clock sysclk -min -0.2 [get_ports sum]

# 异步复位约束
set_max_delay -datapath_only -from [get_ports rst_n] 5.0

// sim/tb_pipeline_adder.v
// testbench：随机激励 + 自动比较

`timescale 1ns/1ps

module tb_pipeline_adder;

    reg         clk, rst_n;
    reg  signed [15:0] a, b;
    wire signed [16:0] sum;
    reg  signed [16:0] sum_ref;
    reg  signed [15:0] a_dly [0:3];
    reg  signed [15:0] b_dly [0:3];
    integer i, errors;

    // 实例化 DUT
    pipeline_adder #(.DATA_WIDTH(16)) dut (
        .clk(clk),
        .rst_n(rst_n),
        .a(a),
        .b(b),
        .sum(sum)
    );

    // 时钟生成：200 MHz
    always #2.5 clk = ~clk;

    initial begin
        clk = 0;
        rst_n = 0;
        a = 0;
        b = 0;
        errors = 0;
        #20 rst_n = 1;  // 释放复位
        #10;

        // 测试 1000 组随机数
        for (i = 0; i < 1000; i = i + 1) begin
            a = $random;
            b = $random;
            sum_ref = a + b;
            // 延迟参考值，与流水线输出对齐
            a_dly[3] <= a_dly[2];
            a_dly[2] <= a_dly[1];
            a_dly[1] <= a_dly[0];
            a_dly[0] <= a;
            b_dly[3] <= b_dly[2];
            b_dly[2] <= b_dly[1];
            b_dly[1] <= b_dly[0];
            b_dly[0] <= b;
            #5;
            // 第 4 个周期后比较
            if (i >= 3) begin
                if (sum !== (a_dly[3] + b_dly[3])) begin
                    $display("ERROR at %0t: a=%0d, b=%0d, sum=%0d, expected=%0d",
                             $time, a_dly[3], b_dly[3], sum, a_dly[3] + b_dly[3]);
                    errors = errors + 1;
                end
            end
        end

        #20;
        if (errors == 0)
            $display("PASS: All 1000 tests passed.");
        else
            $display("FAIL: %0d errors found.", errors);
        $finish;
    end

endmodule