RISC-V FPGA软核在开源EDA工具链中的全流程实现指南（2026 Q2）

// top.v - 顶层模块，例化PicoRV32并连接GPIO/UART
module top (
    input wire clk_12mhz,
    input wire rst_n, // 低有效复位
    output wire [3:0] led,
    output wire uart_tx
);

    // 内部信号
    wire clk;
    wire rst;
    wire [31:0] mem_addr;
    wire [31:0] mem_rdata;
    wire [31:0] mem_wdata;
    wire [3:0] mem_wstrb;
    wire mem_valid;
    wire mem_ready;

    // 时钟与复位同步（简单处理）
    assign clk = clk_12mhz;
    assign rst = ~rst_n;

    // 例化PicoRV32
    picorv32 #(
        .ENABLE_MUL(0),
        .ENABLE_DIV(0),
        .ENABLE_IRQ(0),
        .BARREL_SHIFTER(0),
        .COMPRESSED_ISA(0),
        .CATCH_MISALIGN(1),
        .CATCH_ILLINSN(1),
        .PROGADDR_RESET(32'h0000_0000)
    ) cpu (
        .clk (clk),
        .resetn (rst_n),
        .mem_valid (mem_valid),
        .mem_instr (1'b0),
        .mem_ready (mem_ready),
        .mem_addr (mem_addr),
        .mem_wdata (mem_wdata),
        .mem_wstrb (mem_wstrb),
        .mem_rdata (mem_rdata)
    );

    // 简单内存模型（Block RAM）
    // 此处省略详细实现，见阶段二

    // GPIO输出（低4位驱动LED）
    assign led = mem_wdata[3:0];

    // UART发送器（115200 baud）
    uart_tx #(.BAUD_RATE(115200), .CLK_FREQ(12000000)) uart_inst (
        .clk(clk),
        .rst(rst),
        .tx_data(mem_wdata[7:0]),
        .tx_valid(mem_valid & (mem_addr == 32'h1000_0000)),
        .tx_ready(),
        .tx(uart_tx)
    );

endmodule

// memory.v - 同步双端口RAM，初始化加载程序
module memory (
    input wire clk,
    input wire mem_valid,
    input wire mem_instr,
    output reg mem_ready,
    input wire [31:0] mem_addr,
    input wire [31:0] mem_wdata,
    input wire [3:0] mem_wstrb,
    output reg [31:0] mem_rdata
);

    // 4 KB内存（1024 x 32位）
    reg [31:0] ram [0:1023];

    // 初始化加载程序（使用$readmemh）
    initial begin
        $readmemh("firmware.hex", ram);
    end

    // 写操作（字节使能）
    always @(posedge clk) begin
        if (mem_valid & |mem_wstrb) begin
            if (mem_wstrb[0]) ram[mem_addr[31:2]][7:0] <= mem_wdata[7:0];
            if (mem_wstrb[1]) ram[mem_addr[31:2]][15:8] <= mem_wdata[15:8];
            if (mem_wstrb[2]) ram[mem_addr[31:2]][23:16] <= mem_wdata[23:16];
            if (mem_wstrb[3]) ram[mem_addr[31:2]][31:24] <= mem_wdata[31:24];
        end
    end

    // 读操作（组合逻辑）
    always @(*) begin
        mem_rdata = ram[mem_addr[31:2]];
    end

    // mem_ready：单周期响应
    always @(posedge clk) begin
        mem_ready <= mem_valid;
    end

endmodule

// firmware.c - 测试程序：LED闪烁 + UART输出
volatile unsigned int * const LED_REG = (unsigned int *)0x00000000;
volatile unsigned int * const UART_REG = (unsigned int *)0x10000000;

void delay(volatile int count) {
    while (count--);
}

void main() {
    const char *msg = "Hello, RISC-V!
";
    while (1) {
        // 发送字符串
        const char *p = msg;
        while (*p) {
            *UART_REG = *p++;
            delay(1000);
        }
        // LED闪烁
        *LED_REG = 0x0F;
        delay(500000);
        *LED_REG = 0x00;
        delay(500000);
    }
}

riscv32-unknown-elf-gcc -march=rv32i -mabi=ilp32 -nostdlib -nostartfiles -Ttext=0x00000000 -o firmware.elf firmware.c
riscv32-unknown-elf-objcopy -O binary firmware.elf firmware.bin
# 转换为hex格式（每行一个32位字）
python3 -c "
import sys
with open('firmware.bin', 'rb') as f:
    data = f.read()
    # 填充到4字节对齐
    while len(data) % 4:
        data += b'x00'
    for i in range(0, len(data), 4):
        word = int.from_bytes(data[i:i+4], 'little')
        print(f'{word:08x}')
" > firmware.hex

# synth.ys - Yosys综合脚本
# 读取源文件
read_verilog top.v
read_verilog memory.v
read_verilog picorv32.v
read_verilog uart_tx.v

# 指定顶层模块
synth -top top

# 针对iCE40优化
synth_ice40 -top top -json top.json

# 可选：显示资源统计
stat -top top

# top.lpf - nextpnr引脚约束文件
# 时钟引脚
IO_LOC "clk_12mhz" 35;
IO_TYPE "clk_12mhz" PLL_IN;

# 复位引脚
IO_LOC "rst_n" 49;

# LED输出（4位）
IO_LOC "led[0]" 40;
IO_LOC "led[1]" 41;
IO_LOC "led[2]" 42;
IO_LOC "led[3]" 43;

# UART TX
IO_LOC "uart_tx" 48;

# 综合
yosys -s synth.ys

# 布局布线
nextpnr-ice40 --hx8k --json top.json --pcf top.lpf --asc top.asc

# 生成位流
icepack top.asc top.bin

# 下载到FPGA（使用iceprog）
iceprog top.bin