从零到Offer：2026年FPGA实习生必备技能清单

module uart_tx (
    input  wire       clk,        // 100 MHz 系统时钟
    input  wire       rst_n,      // 低电平复位
    input  wire       start,      // 发送启动信号
    input  wire [7:0] data_in,    // 待发送数据
    output reg        tx,         // 串行输出
    output reg        busy        // 忙标志
);

    parameter BAUD_DIV = 868;     // 100MHz / 115200 ≈ 868
    reg [9:0] cnt;                // 波特率计数器
    reg [3:0] bit_cnt;            // 位计数器 (起始位+8数据位+停止位)
    reg [9:0] shift;              // 移位寄存器

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            tx <= 1'b1;
            busy <= 1'b0;
            cnt <= 0;
            bit_cnt <= 0;
            shift <= 0;
        end else begin
            if (start && !busy) begin
                busy <= 1'b1;
                shift <= {1'b1, data_in, 1'b0}; // 停止位+数据+起始位
                bit_cnt <= 4'd10;
                cnt <= 0;
            end else if (busy) begin
                if (cnt == BAUD_DIV-1) begin
                    cnt <= 0;
                    tx <= shift[0];
                    shift <= {1'b1, shift[9:1]};
                    if (bit_cnt == 4'd1)
                        busy <= 1'b0;
                    else
                        bit_cnt <= bit_cnt - 1;
                end else begin
                    cnt <= cnt + 1;
                end
            end
        end
    end
endmodule

module spi_master (
    input  wire       clk,        // 100 MHz
    input  wire       rst_n,
    input  wire       start,
    input  wire [7:0] data_in,
    output reg [7:0]  data_out,
    output reg        sclk,
    output reg        mosi,
    input  wire       miso,
    output reg        cs_n,
    output reg        busy
);

    parameter CLK_DIV = 2;        // 100MHz / (2*2) = 25MHz SPI时钟
    reg [1:0] cnt;
    reg [2:0] bit_cnt;
    reg [7:0] shift_in, shift_out;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            cs_n <= 1'b1;
            sclk <= 1'b0;
            mosi <= 1'b0;
            busy <= 1'b0;
            cnt <= 0;
            bit_cnt <= 0;
        end else if (start && !busy) begin
            cs_n <= 1'b0;          // 拉低片选
            busy <= 1'b1;
            shift_out <= data_in;
            bit_cnt <= 3'd7;
            cnt <= 0;
        end else if (busy) begin
            if (cnt == CLK_DIV-1) begin
                cnt <= 0;
                sclk <= ~sclk;     // 翻转时钟
                if (sclk) begin    // 下降沿采样
                    shift_in <= {shift_in[6:0], miso};
                end else begin     // 上升沿输出
                    mosi <= shift_out[7];
                    shift_out <= {shift_out[6:0], 1'b0};
                    if (bit_cnt == 0) begin
                        busy <= 1'b0;
                        cs_n <= 1'b1;
                        data_out <= shift_in;
                    end else
                        bit_cnt <= bit_cnt - 1;
                end
            end else
                cnt <= cnt + 1;
        end
    end
endmodule

module pwm_gen (
    input  wire       clk,
    input  wire       rst_n,
    input  wire [7:0] duty,       // 占空比 0-255
    input  wire [15:0] period,    // 周期计数 (决定频率)
    output reg        pwm_out
);

    reg [15:0] cnt;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            cnt <= 0;
            pwm_out <= 1'b0;
        end else begin
            if (cnt >= period) begin
                cnt <= 0;
                pwm_out <= 1'b1;
            end else begin
                cnt <= cnt + 1;
                if (cnt == duty)
                    pwm_out <= 1'b0;
            end
        end
    end
endmodule

module axi_lite_slave (
    input  wire         clk,
    input  wire         rst_n,
    // 写地址通道
    input  wire [31:0]  awaddr,
    input  wire         awvalid,
    output reg          awready,
    // 写数据通道
    input  wire [31:0]  wdata,
    input  wire         wvalid,
    output reg          wready,
    // 写响应通道
    output reg [1:0]    bresp,
    output reg          bvalid,
    input  wire         bready,
    // 读地址通道
    input  wire [31:0]  araddr,
    input  wire         arvalid,
    output reg          arready,
    // 读数据通道
    output reg [31:0]   rdata,
    output reg [1:0]    rresp,
    output reg          rvalid,
    input  wire         rready
);

    // 内部寄存器示例
    reg [31:0] reg0, reg1;

    // 写事务处理
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            awready <= 1'b0;
            wready <= 1'b0;
            bvalid <= 1'b0;
            bresp <= 2'b00;
            reg0 <= 0;
            reg1 <= 0;
        end else begin
            // 地址与数据同时有效时，握手并写入
            if (awvalid && wvalid && !bvalid) begin
                awready <= 1'b1;
                wready <= 1'b1;
                case (awaddr[3:2])  // 按字对齐
                    2'b00: reg0 <= wdata;
                    2'b01: reg1 <= wdata;
                    default: ;
                endcase
                bresp <= 2'b00;  // OKAY
                bvalid <= 1'b1;
            end else if (bvalid && bready) begin
                bvalid <= 1'b0;
                awready <= 1'b0;
                wready <= 1'b0;
            end
        end
    end

    // 读事务处理
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            arready <= 1'b0;
            rvalid <= 1'b0;
            rresp <= 2'b00;
            rdata <= 0;
        end else begin
            if (arvalid && !rvalid) begin
                arready <= 1'b1;
                case (araddr[3:2])
                    2'b00: rdata <= reg0;
                    2'b01: rdata <= reg1;
                    default: rdata <= 0;
                endcase
                rresp <= 2'b00;
                rvalid <= 1'b1;
            end else if (rvalid && rready) begin
                rvalid <= 1'b0;
                arready <= 1'b0;
            end
        end
    end
endmodule