SystemVerilog中interface与modport在复杂总线验证中的高效组织

// 示例：AXI4-Lite Interface
interface axi_lite_if (input logic ACLK, input logic ARESETn);
    // 1. 信号声明
    logic [31:0] AWADDR;
    logic        AWVALID;
    logic        AWREADY;
    logic [31:0] WDATA;
    logic [3:0]  WSTRB;
    logic        WVALID;
    logic        WREADY;
    logic [1:0]  BRESP;
    logic        BVALID;
    logic        BREADY;
    logic [31:0] ARADDR;
    logic        ARVALID;
    logic        ARREADY;
    logic [31:0] RDATA;
    logic [1:0]  RRESP;
    logic        RVALID;
    logic        RREADY;

    // 2. 定义Modport：为主设备和从设备提供不同的信号视角
    modport master_mp (
        output AWADDR, AWVALID, WDATA, WSTRB, WVALID, ARADDR, ARVALID, // 主设备驱动
        input  AWREADY, WREADY, BRESP, BVALID, ARREADY, RDATA, RRESP, RVALID, // 主设备采样
        input  ACLK, ARESETn
    );

    modport slave_mp (
        input  AWADDR, AWVALID, WDATA, WSTRB, WVALID, ARADDR, ARVALID, // 从设备采样
        output AWREADY, WREADY, BRESP, BVALID, ARREADY, RDATA, RRESP, RVALID, // 从设备驱动
        input  ACLK, ARESETn
    );

    // 3. (可选但推荐) 添加时钟块用于同步驱动和采样
    clocking master_cb @(posedge ACLK);
        default input #1step output #0; // 输入在时钟沿前1step采样，输出在时钟沿驱动
        output AWADDR, AWVALID, WDATA, WSTRB, WVALID, ARADDR, ARVALID;
        input  AWREADY, WREADY, BRESP, BVALID, ARREADY, RDATA, RRESP, RVALID;
    endclocking

    // 4. (可选但推荐) 内嵌协议断言
    property p_awvalid_stable;
        @(posedge ACLK) disable iff (!ARESETn)
        $rose(AWVALID) |-> (AWVALID throughout AWREADY[->1]);
    endproperty
    assert_awvalid_stable: assert property (p_awvalid_stable)
        else $error("AWVALID changed before AWREADY asserted.");

endinterface

module reg_file (
    // 传统方式：冗长的端口列表
    // input        ACLK, ARESETn,
    // input [31:0] AWADDR, ...
    // 现代方式：一个interface端口
    axi_lite_if.slave_mp  bus_if
);
    // 在模块内部，通过 bus_if.AWADDR, bus_if.AWVALID 等方式访问信号
    always_ff @(posedge bus_if.ACLK or negedge bus_if.ARESETn) begin
        if (!bus_if.ARESETn) begin
            // 复位逻辑
            bus_if.AWREADY <= 1'b0;
        end else begin
            // 主逻辑，使用 bus_if 下的信号
            if (bus_if.AWVALID && !bus_if.AWREADY) begin
                bus_if.AWREADY <= 1'b1;
            end
        end
    end
endmodule

module tb_top;
    logic clk, rst_n;
    // 1. 生成时钟复位
    initial begin clk=0; forever #5 clk=~clk; end
    initial begin rst_n=0; #100 rst_n=1; end

    // 2. 实例化interface，传入时钟复位
    axi_lite_if bus_if(.ACLK(clk), .ARESETn(rst_n));

    // 3. 实例化DUT，通过modport连接interface
    reg_file u_reg_file (.slave_mp(bus_if));

    // 4. 在UVM环境中，通过config_db传递虚接口
    import uvm_pkg::*;
    initial begin
        uvm_config_db#(virtual axi_lite_if)::set(null, "uvm_test_top.env.agent", "vif", bus_if);
        run_test("base_test");
    end

    // 5. 波形dump
    initial begin
        $dumpfile("waves.vcd");
        $dumpvars(0, tb_top);
    end
endmodule

class axi_lite_driver extends uvm_driver #(axi_lite_seq_item);
    `uvm_component_utils(axi_lite_driver)
    virtual axi_lite_if vif; // 虚接口声明

    task run_phase(uvm_phase phase);
        forever begin
            seq_item_port.get_next_item(req);
            // 使用时钟块同步驱动，避免竞争
            @(vif.master_cb);
            vif.master_cb.AWADDR  <= req.addr;
            vif.master_cb.AWVALID <= 1'b1;
            // 等待握手
            wait(vif.master_cb.AWREADY);
            @(vif.master_cb);
            vif.master_cb.AWVALID <= 1'b0;
            seq_item_port.item_done();
        end
    endtask
endclass