SystemVerilog验证进阶：利用UVM框架搭建FPGA模块验证环境

// File: tb/top_tb.sv
`timescale 1ns/1ps
`include "uvm_macros.svh"
import uvm_pkg::*;

module top_tb;
    // 1. 定义时钟和复位
    logic clk = 0;
    logic rst_n = 0;
    always #5 clk = ~clk; // 100MHz时钟
    initial begin
        #100 rst_n = 1;
    end

    // 2. 声明DUT接口
    my_if dut_if(clk, rst_n); // 假设my_if是定义的虚拟接口

    // 3. 实例化DUT，连接接口
    my_dut u_my_dut (
        .clk   (dut_if.clk),
        .rst_n (dut_if.rst_n),
        .data_i(dut_if.data_i),
        .valid_i(dut_if.valid_i),
        .data_o(dut_if.data_o),
        .valid_o(dut_if.valid_o)
    );

    // 4. 关键步骤：将物理接口通过uvm_config_db传递给UVM环境
    initial begin
        uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.agent", "vif", dut_if);
    end

    // 5. 启动UVM测试
    initial begin
        run_test("base_test");
    end

    // 6. 可选：生成波形文件
    initial begin
        $dumpfile("waves.vcd");
        $dumpvars(0, top_tb);
    end
endmodule

// File: tb/uvm_pkg/my_agent.sv
class my_agent extends uvm_agent;
    `uvm_component_utils(my_agent)

    my_driver    driver;
    my_monitor   monitor;
    uvm_sequencer#(my_transaction) sequencer;

    virtual my_if vif; // 从config_db获取

    function new(string name, uvm_component parent);
        super.new(name, parent);
    endfunction

    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        // 获取虚拟接口
        if(!uvm_config_db#(virtual my_if)::get(this, "", "vif", vif)) begin
            `uvm_fatal("CFG", "Failed to get vif from config_db!")
        end

        monitor = my_monitor::type_id::create("monitor", this);
        monitor.vif = vif; // 直接传递引用

        // 仅在active模式下创建driver和sequencer
        if(get_is_active() == UVM_ACTIVE) begin
            driver = my_driver::type_id::create("driver", this);
            sequencer = uvm_sequencer#(my_transaction)::type_id::create("sequencer", this);
        end
    endfunction

    virtual function void connect_phase(uvm_phase phase);
        super.connect_phase(phase);
        if(get_is_active() == UVM_ACTIVE) begin
            driver.seq_item_port.connect(sequencer.seq_item_export);
            driver.vif = vif;
        end
    endfunction
endclass

// File: tb/uvm_pkg/my_sequence.sv
class my_sequence extends uvm_sequence#(my_transaction);
    `uvm_object_utils(my_sequence)
    rand int num_trans = 10; // 可随机化的测试长度

    function new(string name="my_sequence");
        super.new(name);
    endfunction

    virtual task body();
        `uvm_info(get_type_name(), $sformatf("Starting sequence, num_trans=%0d", num_trans), UVM_LOW)
        repeat(num_trans) begin
            `uvm_do(req) // 自动创建、随机化并发送transaction
        end
    endtask
endclass

// File: tb/uvm_pkg/my_scoreboard.sv
class my_scoreboard extends uvm_scoreboard;
    `uvm_component_utils(my_scoreboard)
    uvm_analysis_imp#(my_transaction, my_scoreboard) item_collected_export;

    my_transaction ref_q[$]; // 期望队列

    function new(string name, uvm_component parent);
        super.new(name, parent);
        item_collected_export = new("item_collected_export", this);
    endfunction

    // 从monitor接收实际DUT输出
    virtual function void write(my_transaction tr);
        my_transaction ref_tr;
        // 简单比对：查找并移除匹配的期望事务
        foreach(ref_q[i]) begin
            if(ref_q[i].compare(tr)) begin
                ref_q.delete(i);
                `uvm_info("SCBD", "Transaction matched!", UVM_LOW)
                return;
            end
        end
        `uvm_error("SCBD", $sformatf("Unexpected transaction received: %s", tr.convert2string()))
    endfunction

    // 从reference model或driver侧接收期望输出
    function void add_expected(ref_tr);
        ref_q.push_back(ref_tr);
    endfunction

    // 在report_phase检查队列是否清空
    virtual function void report_phase(uvm_phase phase);
        if(ref_q.size() != 0)
            `uvm_error("SCBD", $sformatf("Scoreboard has %0d unmatched transactions", ref_q.size()))
    endfunction
endclass