报错信息[[DRC BIVC-1] the following port in this bank have conflicting VCCOs: sys_clk (LVCMOS18,requiring VCCO=1.800)。
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报错信息[[DRC BIVC-1]
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{"0":{"name":"paragraph","html":{"component":"p","class":"","content":"\u539f\u56e0\uff1a\u7ba1\u811a\u672a\u505a\u7ea6\u675f\u3002<\/span>"},"attrs":[]},"2":{"name":"paragraph","html":{"component":"p","class":"","content":"\u63aa\u65bd\uff1a\u53ef\u4ee5\u5728XDC\u7ea6\u675f\u6587\u4ef6\u4e2d\u52a0\u5165\u65f6\u949f\u7ea6\u675f\uff1aset_property IOSTANDARD LVCMOS33 [get_ports sys_clk] set_property PACKAGE_PIN R4 [get_ports sys_clk]\u3002<\/span>"},"attrs":[]},"4":{"name":"paragraph","html":{"component":"p","class":"","content":"\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014\u2014<\/span>"},"attrs":[]},"6":{"name":"heading","html":{"level":"h1","class":"wp-block-heading","id":"","title":"vivado\uff1a[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34."},"attrs":{"level":1}},"8":{"name":"paragraph","html":{"component":"p","class":"","content":"\u62a5\u9519\uff1a"},"attrs":[]},"10":{"name":"code","html":"[USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'F:\/vivado_project\/timer\/timer.sim\/sim_1\/behav\/xsim\/elaborate.log' file for more information.\n[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.","attrs":[]},"12":{"name":"code","html":"[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs: \nclk (LVCMOS18, requiring VCCO=1.800) and a_to_g[0] (LVCMOS33, requiring VCCO=3.300)","attrs":[]},"14":{"name":"code","html":"[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.","attrs":[]},"16":{"name":"paragraph","html":{"component":"p","class":"","content":"\u539f\u56e0\uff1a"},"attrs":[]},"18":{"name":"paragraph","html":{"component":"p","class":"","content":"clk\u53cadp\u7684VCCOS\u4e3a\u9ed8\u8ba4\u7684LVCMOS18\uff0c\u672a\u8fdb\u884c\u66f4\u6539\u3002"},"attrs":[]},"20":{"name":"paragraph","html":{"component":"p","class":"","content":"\u89e3\u51b3\uff1a"},"attrs":[]},"22":{"name":"image","html":{"title":"\u56de\u7b54\u7ed9\uff1a\u62a5\u9519\u4fe1\u606f[[DRC BIVC-1] – 2025-11-09 22:48:39 - \u7b2c1\u5f20 - FPGA\u7ebf\u4e0a\u8bfe\u7a0b\u5e73\u53f0\uff5c\u6700\u5168\u6808\u7684FPGA\u5b66\u4e60\u5e73\u53f0\uff5cFPGA\u5de5\u7a0b\u5e08\u8ba4\u8bc1\u57f9\u8bad","src":"https:\/\/admin.shaonianxue.cn\/wp-content\/uploads\/2025\/11\/image-2025-11-09-14-48-27-22.png","alt":"\u56de\u7b54\u7ed9\uff1a\u62a5\u9519\u4fe1\u606f[[DRC BIVC-1] – 2025-11-09 22:48:39 - \u7b2c1\u5f20"},"attrs":[]},"24":{"name":"paragraph","html":{"component":"p","class":"","content":""},"attrs":[]}}
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