报错信息[[DRC BIVC-1] the following port in this bank have conflicting VCCOs: sys_clk (LVCMOS18,requiring VCCO=1.800)。
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原因：管脚未做约束。
措施：可以在XDC约束文件中加入时钟约束：set_property IOSTANDARD LVCMOS33 [get_ports sys_clk] set_property PACKAGE_PIN R4 [get_ports sys_clk]。
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vivado：[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34.
报错：
[USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'F:/vivado_project/timer/timer.sim/sim_1/behav/xsim/elaborate.log' file for more information.
[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
clk (LVCMOS18, requiring VCCO=1.800) and a_to_g[0] (LVCMOS33, requiring VCCO=3.300)[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.原因：
clk及dp的VCCOS为默认的LVCMOS18，未进行更改。
解决：
