基于FPGA的广告点阵屏(学员作品展示)

基于FPGA的广告点阵屏(学员作品展示) - 第1张
基于FPGA的广告点阵屏(学员作品展示) - 第2张
基于FPGA的广告点阵屏(学员作品展示) - 第3张
基于FPGA的广告点阵屏(学员作品展示) - 第4张

verilog代码:(注意格式)

  1. `timescale 1ns / 1ps
  2. module HC_595
  3. #(
  4. parameter SYSCLK = 50_000_000,//系统时钟频率
  5. parameter CLK_HZ = 100_000 //用系统时钟产生一个100k的频率的时钟
  6. )
  7. (
  8. input sysclk ,
  9. input rst_n ,
  10. input [15:0] Data ,
  11. input en ,//开始信号
  12. output reg SCK ,
  13. output reg RCK ,
  14. output reg DA ,
  15. output reg Done //结束信号
  16. );
  17. localparam DELAY = SYSCLK/CLK_HZ;
  18. localparam MID = DELAY/2;
  19. reg [31:0] cnt_delay;
  20. reg [31:0] cnt_mid;
  21. reg [1:0] en_temp;
  22. reg [15:0] data_temp;//用于存储输入进来的16bit数据
  23. localparam IDLE = 3'b001,
  24. DATA = 3'b010,
  25. STOP = 3'b100;
  26. reg [2:0] cur_state,next_state;
  27. reg [4:0] cnt_bit;
  28. //______________________________滤除毛刺__________________________________//
  29. always@(posedge sysclk)
  30. if(!rst_n)
  31. en_temp <= 2'b00;
  32. else
  33. en_temp <= {en_temp[0],en};
  34. //___________________________DELAY__________________________________//
  35. always@(posedge sysclk)
  36. if(!rst_n)
  37. cnt_delay <= 32'd0;
  38. else if(cnt_delay >= DELAY - 1 )
  39. cnt_delay <= 32'd0;
  40. else cnt_delay <= cnt_delay + 32'd1;
  41. //___________________________MID__________________________________//
  42. always@(posedge sysclk)
  43. if(!rst_n)
  44. cnt_mid <= 32'd0;
  45. else if(cnt_mid >= MID - 1 )
  46. cnt_mid <= 32'd0;
  47. else
  48. cnt_mid <= cnt_mid + 32'd1;
  49. //______________________________产生SCK__________________________________//
  50. always@(posedge sysclk)
  51. if(!rst_n)
  52. SCK <= 1'b0;
  53. else if(cnt_mid >= MID - 1)
  54. SCK <= ~SCK;
  55. else
  56. SCK <= SCK;
  57. //_________________________state1____________________________________//
  58. always@(posedge sysclk)
  59. if(!rst_n)
  60. cur_state <= IDLE;
  61. else
  62. cur_state <= next_state;
  63. //_______________________________state2_____________________________________//
  64. always@(*)
  65. case(cur_state)
  66. IDLE:begin
  67. if(en_temp == 2'b01 ) //开始信号稳定的时候跳到数据状态去传输数据
  68. next_state = DATA;
  69. else
  70. next_state = cur_state;
  71. end
  72. DATA:begin
  73. if(cnt_bit == 5'd16 && cnt_delay >= DELAY - 1)
  74. next_state = STOP;
  75. else
  76. next_state = cur_state;
  77. end
  78. STOP:begin
  79. if(cnt_delay >= DELAY - 1)
  80. next_state = IDLE;
  81. else
  82. next_state = cur_state;
  83. end
  84. endcase
  85. //__________________________state3_________________________________//
  86. always@(posedge sysclk)
  87. if(!rst_n)begin
  88. cnt_bit <= 5'd0;
  89. RCK <= 1'b0;
  90. data_temp <= 16'd0;
  91. Done <= 1'b0;
  92. DA <= 1'b0;
  93. end
  94. elsecase(cur_state)
  95. IDLE:begin
  96. cnt_bit <= 5'd0;
  97. RCK <= 1'b0;
  98. data_temp <= Data;
  99. Done <= 1'b0;
  100. DA <= 1'b0;
  101. end
  102. DATA:begin
  103. if(cnt_delay >= DELAY - 1)begin
  104. DA <= data_temp[15];
  105. data_temp <= {data_temp[14:0],1'b0};
  106. end
  107. else begin
  108. DA <= DA;
  109. data_temp <= data_temp;
  110. end
  111. if(cnt_delay >= DELAY - 1 && cnt_bit >= 5'd16)
  112. cnt_bit <= 5'd0;
  113. else if(cnt_delay >= DELAY - 1)
  114. cnt_bit <= cnt_bit + 5'd1;
  115. else
  116. cnt_bit <= cnt_bit;
  117. Done <= 1'b0;
  118. RCK <= 1'b0;
  119. end
  120. STOP:begin
  121. if(cnt_delay == 1)
  122. RCK <= 1'b1;
  123. else
  124. RCK <= 1'b0;
  125. if(cnt_delay >= DELAY - 1)
  126. Done <= 1'b1;
  127. else
  128. Done <= 1'b0;
  129. cnt_bit <= 5'd0;
  130. end
  131. endcase
  132. endmodule
本文原创,作者:二牛学FPGA,其版权均为FPGA线上课程平台|最全栈的FPGA学习平台|FPGA工程师认证培训所有。
如需转载,请注明出处:https://z.shaonianxue.cn/9345.html

"愿我的文字能带给您一丝美好"

还没有人赞赏,支持一下

评论

A 为本文作者,G 为游客总数:0
加载中…

提交评论

游客,您好,欢迎参与讨论。

我的购物车

购物车为空

优惠券

没有优惠券